Field of the Invention
The present invention relates to a semiconductor device and a method for producing a semiconductor device.
Description of the Related Art
In recent years, phase-change memories have been developed (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404 and its counterpart U.S. Pat. No. 9,025,369 B2). Such a phase-change memory records changes in the resistances of information memory elements in memory cells to thereby store information.
The phase-change memory uses the following mechanism: turning on a cell transistor causes a current to pass between a bit line and a source line; this causes a high-resistance-element heater to generate heat; this melts chalcogenide glass (GST: Ge2Sb2Te5) in contact with the heater to thereby cause a state transition. Chalcogenide glass that is melted at a high temperature (with a large current) and rapidly cooled (by stopping the current) is brought to an amorphous state (Reset operation). On the other hand, chalcogenide glass that is melted at a relatively-low high temperature (with a small current) and slowly cooled (with a gradual decrease in the current) is brought to crystallization (Set operation). Thus, at the time of reading information, the binary information (“0” or “1”) is determined on the basis of whether a large current passes between the bit line and the source line (a low resistance, that is, the crystalline state) or a small current passes (a high resistance, that is, the amorphous state) (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404 and U.S. Pat. No. 9,025,369 B2).
In this case, for example, a very large reset current of 200 μA passes. In order to pass such a large reset current through cell transistors, the memory cells need to have a considerably large size. In order to pass such a large current, selection elements such as bipolar transistors and diodes can be used (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404 and U.S. Pat. No. 9,025,369 B2).
A diode is a two-terminal element. Thus, when one source line is selected for the purpose of selecting a memory cell, the current of all the memory cells connected to the one source line passes through the one source line. This results in a large IR drop, which is a voltage drop equal to the product of IR (current and resistance), in the source line.
On the other hand, a bipolar transistor is a three-terminal element. However, a current passes through the gate, which makes it difficult to connect a large number of transistors to the word line.
By reducing the area of the cross sections (in the current flow direction) of a GST film and a heater element, the reset current and the read current can be decreased. In an existing example, a heater element is formed on a side wall of the gate of a planar transistor and a GST film is formed on the gate, to thereby reduce the area of the cross sections (in the current flow direction) of the GST film and the heater element. This method requires cell strings with which a plurality of cells constituted by planar transistors are connected in series (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-204404 and U.S. Pat. No. 9,025,369 B2).
A Surrounding Gate Transistor (hereafter, referred to as an “SGT”) has been proposed that has a structure in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer. SGTs allow a larger current per unit gate width to pass than double-gate transistors (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-356314 and its counterpart U.S. Publication US 2004/0262681 A1). In addition, SGTs have a structure in which the gate electrode surrounds the pillar-shaped semiconductor layer. Thus, the gate width per unit area can be increased, so that an even larger current can be passed.
In a phase-change memory, a large reset current is used and hence the resistance of the source line needs to be decreased.
In existing MOS transistors, in order to successfully perform a metal gate process and a high-temperature process, a metal gate-last process of forming a metal gate after a high-temperature process is used (for example, refer to IEDM2007 K. Mistry et. al, pp 247-250). In this process, a gate is formed of polysilicon; an interlayer insulating film is subsequently deposited; chemical mechanical polishing is then performed to expose the polysilicon gate; the polysilicon gate is etched; and metal is subsequently deposited. Thus, also in the production of an SGT, in order to successfully perform a metal gate process and a high-temperature process, a metal gate-last process of forming a metal gate after a high-temperature process needs to be used.
In the metal gate-last process, after a polysilicon gate is formed, a diffusion layer is formed by ion implantation. However, in an SGT, the upper portion of the pillar-shaped silicon layer is covered with a polysilicon gate. Accordingly, it is necessary to find a way to form the diffusion layer.
Silicon has a density of about 5×1022 atoms/cm3. Accordingly, for narrow silicon pillars, it is difficult to make impurities be present within the silicon pillars.
In existing SGTs, it has been proposed that, while the channel concentration is set to a low impurity concentration of 1017 cm−3 or less, the work function of the gate material is changed to adjust the threshold voltage (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-356314 and U.S. Publication US 2004/0262681 A1).
A planar MOS transistor has been disclosed in which a sidewall on an LDD region is formed of a polycrystalline silicon of the same conductivity type as that of the lightly doped layer and the surface carriers of the LDD region are induced by the work-function difference between the sidewall and the LDD region, so that the impedance of the LDD region can be reduced, compared with oxide film sidewall LDD MOS transistors (for example, refer to Japanese Unexamined Patent Application Publication No. 11-297984). This publication states that the polycrystalline silicon sidewall is electrically insulated from the gate electrode. This publication also shows that, in a drawing, the polycrystalline silicon sidewall and the source-drain are insulated from each other with an interlayer insulating film.